1. Field of the Invention
The present disclosure relates to an array substrate for a display panel and a method for manufacturing thereof. More specifically, the present disclosure relates to a structure and a method capable of preventing a damage of a substrate due to static electricity in a display panel with a gate-in-panel (GIP) structure.
2. Description of the Prior Art
As information oriented society has been developed, demands for displays for displaying an image are increasing. Thus, various flat displays such as a liquid crystal display (LCD), a plasma display panel (PDP), and organic light, emitting display (OLED) have been used recently.
Active matrix type liquid crystal displays among the liquid crystal display including an array substrate including a thin film transistor (TFT) as a switching device for controlling an on/off state of voltage for each pixel have been generally used.
Such active matrix type liquid crystal display includes a liquid crystal panel including the array substrate including a thin film transistor (TFT) as a switching device for controlling an on/off state of voltage for each pixel and a color filter substrate including a color filter, and a liquid crystal layer interposed between the array substrate and the color filter substrate. The liquid crystal display further implements a driver having a driving circuit to drive the liquid crystal panel.
The driver is generally embodied on a driving printed-circuit-board (PCB). The driving PCB can be divided into a gate driving PCB connected to gate lines on the liquid crystal panel, and a data driving PCB connected to data lines of the liquid crystal panel.
Also, the gate driving PCB is connected to a gate pad portion (i) formed in an edge of the liquid crystal panel and (ii) connected to the gate lines. The data driving PCB is connected to a data pad portion (i) formed in another edge of the liquid crystal panel perpendicular to the edge with the gate pad portion and (ii) connected to the data lines. Such gate and data driving PCBs are mounted on the liquid crystal panel by using, for example, a tape carrier package (TCP) or a Flexible Printed Circuit (FPC).
However, the driving PCB, which is divided into the gate and data driving PCBs and loaded on the gate and data pad portions, causes the size and weight of the liquid crystal display to increase.
To address this matter, the liquid crystal display with a gate-in-panel (GIP) structure has been proposed which allows only one driving PCB to be loaded on one edge of the liquid crystal panel with the gate driving circuit directly formed on the liquid crystal panel.
FIG. 1 is a circuitry diagram schematically showing an array substrate included in a liquid crystal display with a GIP structure according to the related art.
As shown in FIG. 1, the array substrate of the liquid crystal display with the GIP structure is divided into an active area AA used to display images and a non-active area NA configured to surround the active area AA.
The active area AA includes gate line GL and data line DL configured to cross each other and to define pixel regions P, thin film transistors TR, each connected to the respective gate line GL and data line DL, and pixel electrodes PXL connected to the respective thin film transistors TR.
On the other hand, a part of the non-active area adjacent to a top edge of the active area AA includes a plurality of circuit films (not shown) divisionally loaded with a data driver (not shown). Another part of the non-active area adjacent to one of both side edges of the active area AA includes a gate driving circuit GCA and a signal input portion SIA positioned adjacent to an edge of the gate driving circuit GCA.
The gate driving circuit GCA is configured with a plurality of circuit blocks CB1 and CB2, and each of the plurality of circuit blocks CB1 and CB2 includes a plurality of switching elements, capacitors, and so on. One circuit block CB1 of the circuit blocks is connected to the gate lines formed in the active area AA and many kinds of signal lines CL1 to CL4 formed in the signal input portion SIA.
In this specification, a line extending from the data driving circuit or driver over the entire panel in parallel with the data lines and transferring various signals to the gate driving circuit GCA may be referred to as a signal input area (SIA). The line(s) included in the signal input area SIA may be referred to as a signal line(s).
A connecting line to connect between the signal line included in such signal input area SIA and the circuit block of the gate driving circuit GCA may be generally referred to as a gate link line (GLL).
The signal line included in such signal input area SIA may be a metal line patterned by the gate metal layer extending from the data driving circuit or driver to a top of the panel, namely over the entire panel. Meanwhile, static electricity may be generated in manufacturing the signal lines of a gate metal pattern due to friction or contacts between the manufacturing device and the panel and the like, and a large amount electric charge may be kept or charged at the gate metal pattern of such signal lines. During the next processes for forming the source/drain metal layer and so on, the electrical charge maintained at the signal line pattern may be transferred over to the source/drain metal layer.
As a result, the static electricity generated in manufacturing process of patterning the signal lines and gate metal layer may destroy an insulating layer such as a gate insulating layer between the gate metal layer and source/drain metal layer so that a gate metal layer and a source/drain metal layer may be short-circuited.
That is, during manufacturing the display panel with the GIP structure, specific signal line of the GIP is formed of a metal such as the gate metal pattern and longitudinally extends over the entire panel so that the quantity of the electric charge stored on such signal line may become too large. Therefore, the static electricity generated in manufacturing process of the signal line may damage a part of the display panel during the following manufacturing processes.